Clock gating analyzing apparatus, clock gating analyzing...

Details Clock gating analyzing apparatus, clock gating analyzing... Clock gating analyzing apparatus, clock gating analyzing...

2007-12-17

2011-11-29

Rodriguez, Paul (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S013000, C703S014000

Reexamination Certificate

active

08069026

ABSTRACT:
Clock gating analysis of a target circuit having a plurality of clock gates, involves the calculation of a clock gate function for each of the clock gates. The clock gate functions indicate an activation state of the clock gates and a combination of output values from sequential circuit elements in the target circuit are substituted into each of the clock gate functions to obtained clock gate function values. Combinations of the clock gate function values form individual clock gating states. Each clock gating state indicates an activation state of each of the local clocks, collectively. A table indicating correlations between the combinations of output values and the clock gating states is generated and from the conversion table, a group that includes all of the clock gating states possible is output.

REFERENCES:
patent: 6035112 (2000-03-01), Kito
patent: 6202166 (2001-03-01), Tang
patent: 6557150 (2003-04-01), Honmura
patent: 2006/0085713 (2006-04-01), Takabatake
patent: A 8-202569 (1996-08-01), None
patent: 09-251483 (1997-09-01), None
patent: A 10-283381 (1998-10-01), None
patent: A 11-259554 (1999-09-01), None
patent: 2006-106865 (2006-04-01), None
patent: WO 99/09497 (1999-02-01), None
Higuchi et al. “A Fast State Reduction Alogrithm for Incompletely Specified Finite State Machines”, 1996 ACM. 4 pages.
Benini et al. “Automatic Synthesis of Low-Power Gated-Clock Finite-State Machine” IEEE 1996. p. 630-643.
Benini et al. “Design for testablity of gated-clock FSMs”, IEEE 1996. p. 589-596.
Benini et al. “Symbolic Synthesis of clock-Gating Logic for Power Optimization of control-Oriented Synchronous Networks”, IEEE1997., p. 514-520.
Physics3330. “Digital Electronics I: Logic, Flip-Flops, and Clocks”, http://www.colorado.edu/physics/phys3330/phys3330—fa05/manual/Exp—9.pdf. 2005.
M. Kawarabayashi et al., “A Verification Technique for Gated Clock,” Proceedings of the Design Automation Conference, pp. 123-127, 1993.

Affiliated with

Also associated with

Rating

Clock gating analyzing apparatus, clock gating analyzing... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock gating analyzing apparatus, clock gating analyzing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock gating analyzing apparatus, clock gating analyzing... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4292631