Clock gater circuit

Details Clock gater circuit Clock gater circuit

2003-01-21

2004-10-26

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform amplitude control

C327S175000, C327S365000

Reexamination Certificate

active

06809570

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention generally relates to clock gater circuits. More particularly, and not by way of any limitation, the present invention is directed to a clock gater having a reduced set-up time for a qualifier signal thereof with no area impact.
2. Description of Related Art
Many, if not most, of the integrated circuits (“ICs”) currently being produced include some number of clocked logic circuits. A clocked logic circuit is one that performs its function subsequent to the assertion (or deassertion) of a clock signal. For example, some logic circuits (e.g., static logic circuits) cannot perform their intended functions until a clocked enable signal is asserted. Other logic gates (e.g., certain dynamic logic circuits) are alternately precharged and enabled by a clock signal and can only perform their intended functions during the enable phase of the clock signal.
Large-scale microprocessor ICs are designed to include clock distribution systems for distributing clock signals to various circuits on the IC and implement an overall clocking strategy. Typically, such clock distribution systems include devices called “clock gaters,” or simply “gaters”. Gaters buffer the clock signal, restoring strength thereto so that it is capable of driving a circuit.
It will be recognized that, in some instances (e.g., in order to conserve power or reduce heat generation), it will be necessary to inhibit operation of one or more circuits on the IC chip for a predetermined number of clock cycles while the remainder of the chip continues to function. In this regard, clock gaters can function as a simple on/off switch for the clock, controlling whether or not the clock signal flows through to the clocked circuit, thereby controlling whether or not the circuit operates.
FIG. 1A
is a schematic diagram of a conventional prior art clock gater circuit
100
. The gater circuit
100
includes an independently-controlled push-pull inverter
102
to create an output clock signal (“CK”) from an input clock signal (“SLCBO”). In particular, an push control signal NPU is connected to a PFET
104
a
of the inverter
102
; this comprises the “push” structure. Similarly, a pull control signal PD is connected to an nFET
104
b
of the inverter
102
; this comprises the “pull” structure. In normal operation, a signal output from the inverter
102
flips up or down depending on the state of the push and pull control signals.
A qualifier (“QUALH”) signal, latched by a gate
106
, can enable or disable the pull control signal PD on the push-pull inverter
102
, thus respectively enabling or disabling the flow of the clock signal through the circuit
100
. The primary problem with the clock gater circuit
100
is that the set-up time, that is, the amount of time prior to the firing of the input clock the QUALH signal needs to be asserted or deasserted, is significant. As a result, if the QUALH signal does not transition sufficiently early relative to the input clock signal, the output clock signal CK will not be enabled or disabled as desired. In the case of failure to disable the clock, this can result unnecessary power consumption and heat generation. Additionally, if the qualifier signal is too late or too early (i.e., does not meet timing requirements), the resulting extra or nonexistent clock could cause the processor to perform a calculation incorrectly.
FIG. 1B
is a gate level block diagram of the circuit
100
. As best shown in
FIG. 1B
, the input clock signal SLCBO is delayed by a gate
120
to form a delayed clock signal ckd, which in turn is NANDed with the QUALH signal by a NAND gate
122
to produce an FBN signal. The FBN signal is NORed with the input clock signal SLCBO by a NOR gate
124
to produce the pull down control signal PD, which is applied to the gate of the FET
104
b
. The output clock signal is fed back and NANDed with the input clock signal SLCBO by a NAND gate
126
to produce the push up control signal NPU, which is applied to the gate of the FET
104
a
. The drains of the FETs
104
a
,
104
b
, designated as an nck node
127
, are connected to the input of an inverter
128
, the output of which comprises the output clock signal CK. The output of the inverter
128
is connected to the input of a second inverter
130
, the output of which is connected to the input of the inverter
128
to form a feedback loop.
Operation of the gater circuit
100
is illustrated in a timing diagram in FIG.
2
. As illustrated in
FIG. 2
, a waveform
200
represents the voltage level (from 0.0 V to 1.2V) of the input clock signal SLCBO over time (in nanoseconds (“ns”). Two and a half cycles of the input clock SLCBO comprising three rising edges
201
a
,
201
b
, and
201
c
, and two falling edges
202
a
,
202
b
, are illustrated in FIG.
2
. Waveforms
204
a
and
204
b
represent QUALH signals asserted and subsequently deasserted at different points in time with respect to the input clock signal SLCBO. In particular, the QUALH signal represented by the waveform
204
a
is asserted and subsequently deasserted approximately 10 ps earlier in time than the QUALH signal represented by the waveform
204
b.
As will be noted with reference to
FIG. 2
, the earlier QUALH signal, represented by waveform
204
a
, is asserted (as represented by a rising edge
205
a
thereof) a time t1 after the immediately preceding falling edge
202
a
of the input clock signal SLCBO (waveform
200
). Because the length of time t1 is short enough to meet the set-up time requirements, the next cycle of the output clock signal CK is enabled, as represented by a waveform
208
a
. In contrast, the later QUALH signal, represented by waveform
204
b
, is asserted (as represented by a rising edge
205
b
thereof) a time t2 after the immediately preceding falling edge
202
b
of the input clock signal SLCBO (waveform
200
). In this case, because the length of time t2 does not meet set-up time requirements, the next cycle of output clock signal CK is suppressed, as represented by a waveform
208
b.
Similarly, the first QUALH signal (waveform
204
a
) is deasserted (as represented by a falling edge
210
a
thereof) a time t3 after the immediately preceding falling edge
202
b
of the input clock signal SLCBO (waveform
200
). Because the length of time t3 meets the set-up time requirements, the deassertion of the QUALH signal results in suppression of the next cycle of the output clock signal CK, as represented by a waveform
212
a
. In contrast, the second QUALH signal (waveform
204
b
) is deasserted (as represented by a falling edge
210
b
thereof) a time t4 after the immediately preceding falling edge
202
b
of the input clock signal SLCBO (waveform
200
). Because the length of time t4 does not meet the set-up time requirements, the deassertion of the QUALH signal results fails to suppress the next cycle of the output clock signal CK, as represented by a waveform
212
b.
FIG. 2
illustrates the concept of negative set-up time. In particular, a positive set-up time indicates a point in time prior to firing of the input clock signal within which the QUALH signal must be asserted/deasserted in order to respectively enable/disable the output clock signal. A negative set-up time indicates a point in time following firing of the input clock signal before which the QUALH signal must be asserted/deasserted in order to respectively enable/disable the output clock signal for the immediately succeeding cycle. In the examples shown in
FIG. 2
, the set-up time is approximately −70 picoseconds (“ps”), meaning that the QUALH signal must be asserted/deasserted before 70 ps after the firing of the input clock signal in order to effectively enable/disable the output clock signal for the immediately succeeding cycle. As shown in
FIG. 2
, times t1 and t3 meet the set-up time requirements (i.e., are less than or equal to 70 ps); times t2 and t4 do not (i.e., are greater than 70 ps).
FIG. 3
illustrates a timing diagram that is identical to the timing diagram illustrated in
FI

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