Clock gated digital data encoding circuit

Details Clock gated digital data encoding circuit Clock gated digital data encoding circuit

1975-04-17

1976-04-20

Robinson, Thomas A.

Communications: electrical

Audible indication

Percussion-type sound producer

179 15A, H03K 1324, H04J 600

Patent

active

039522989

ABSTRACT:
A digital data encoding circuit for use in a one-way transmission system utilizes three 8-bit multiplexers to generate and transmit a 64-bit message. Each bit in the message comprises a 4-chip, or time slot, code that includes an embedded clock therein. The encoding circuit repetitively generates the 64-bit coded message but only enables transmission of one message during periodically recurring intervals. In the event a priority message is sensed, the time between the intervals is reduced so that the rate of message transmission is increased.

REFERENCES:
patent: 3300759 (1967-01-01), Chapman et al.
patent: 3697698 (1972-10-01), Oswald et al.
patent: 3833757 (1974-09-01), Kirk et al.
patent: 3860908 (1975-01-01), Stratton

Affiliated with

Also associated with

Rating

Clock gated digital data encoding circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock gated digital data encoding circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock gated digital data encoding circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1590699