Clock frequency synthesis using delay-locked loop

Details Clock frequency synthesis using delay-locked loop Clock frequency synthesis using delay-locked loop

1997-08-29

1998-09-08

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327265, 327261, 327149, 327158, H03K 513, H03K 5159

Patent

active

058050035

ABSTRACT:
A circuit for synthesizing, from a first signal having a first frequency, a second signal having a second frequency. This synthesis includes using a delay locked loop in combination with a minimal amount of logic circuitry to generate a synthesized output signal which is completely deterministic and does not require any analog control.

REFERENCES:
patent: 4338531 (1982-07-01), Corso
patent: 4626716 (1986-12-01), Miki
patent: 5463337 (1995-10-01), Leonowich
patent: 5491673 (1996-02-01), Okayasu
patent: 5521499 (1996-05-01), Goldenberg et al.

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