Clock frequency multiplication device

Details Clock frequency multiplication device Clock frequency multiplication device

1996-09-05

1998-12-29

Malzahn, David H.

Boots, shoes, and leggings

377 47, G06F 768

Patent

active

058547550

ABSTRACT:
A clock frequency multiplication device comprising a first multiplier for generating an oscillating frequency every first half of a period of an input clock signal where the input clock signal is high in logic, counting the oscillating frequency, dividing the resultant count data at a division ratio of 1/2.sup.n, where n is a natural number, providing the divided count data as a preset signal and down counting the count data in response to the preset signal to multiply the frequency of the input clock signal by a desired number for the first half of the period of the input clock signal, a second multiplier for multiplying the frequency of the input clock signal by the desired number for the latter half of the period of the input clock signal where the input clock signal is low in logic, in the same manner as that of the first multiplier, a control unit for controlling the first and second multipliers in such a manner that they can be operated for the opposite halves of the period of the input clock signal and setting the division ratio of the first and second multipliers to control a multiplication ratio thereof, and an output stage for mixing output signals from the first and second multipliers and outputting the mixed result as a multiplied frequency clock signal.

REFERENCES:
patent: 3970954 (1976-07-01), Even
patent: 4244027 (1981-01-01), Shai
patent: 4773031 (1988-09-01), Tobin
patent: 4956797 (1990-09-01), Berard
patent: 5422835 (1995-06-01), Houle
patent: 5719510 (1998-02-01), Weidner

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