Clock frequency doubler

Details Clock frequency doubler Clock frequency doubler

1991-02-12

1992-05-05

Pascal, Robert J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328 20, H03K 300

Patent

active

051110660

ABSTRACT:
A circuit for generating non-overlapping complementary clock signals at a double frequency from an input clock signal. An NAND flip-flop (2) has complementary outputs on which double frequency signals are available. A D-type flip-flop (3) receives on its clock input (H) one of the outputs of the NAND flip-flop, and has its output (Q.sub.D) coupled to its data input (D) through an inverter. Two Exclusive OR gates (XO1, XO2) receive on their first inputs the input clock signal and its complement, respectively, and on their second input the output of the D-type flip-flop. The outputs of the OR gates are connected to the inputs (E1 and E2) of the NAND flip-flop, respectively.

REFERENCES:
patent: 4634987 (1987-01-01), Nolte
Fisher, "Frequency Doubler from Clock-Pulse Reconstructer", Electronic Engineering, Aug. 1975, p. 7.
IBM Technical Disclosure Bulletin, vol. 29, No. 1, Jun. 1986.
Electrical Design News Article by Giboney, entitled "Double-Edge Pulser Uses Few Parts", vol. 17, 1972.

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