Clock frequency dividing circuit

Details Clock frequency dividing circuit Clock frequency dividing circuit

2011-01-04

2011-01-04

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S115000, C327S202000, C327S203000

Reexamination Certificate

active

07863948

ABSTRACT:
A first frequency dividing circuit and a second frequency dividing circuit are provided, and these circuits frequency-divide two-phase external clocks injected from an external part, to output four-phase clocks with phase guarantee. Each of the frequency dividing circuits includes a mixer, an adding circuit, and a phase circuit. The first frequency dividing circuit and the second frequency dividing circuit are coupled in loop shape via a first coupling circuit and a second coupling circuit. The first coupling circuit receives a first output signal of the first frequency dividing circuit to output a second external input signal to the second frequency dividing circuit, and the second coupling circuit receives a second output signal of the second frequency dividing circuit to output a first external input signal to the first frequency dividing circuit, and a clock frequency dividing circuit with a high loop gain and a wide lock range can be realized.

REFERENCES:
patent: 7304519 (2007-12-01), Neubauer
patent: 2006/0208776 (2006-09-01), Tonietto et al.
patent: 05-347554 (1993-12-01), None
Hamid R. Rategh et al., A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for 5-GHz Wireless LAN Receiver, IEEE Journal on Solid-State Circuits, vol. 35, No. 5, May 2000, pp. 780-781.
A. Mazzanti et al., Injection Locking LC Dividers for low Power Quadrature Generation, IEEE 2003 Custom Integrated Circuits Conference,pp. 563-566.

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