Clock frequency divider circuit and method of dividing clock...

Details Clock frequency divider circuit and method of dividing clock... Clock frequency divider circuit and method of dividing clock...

2007-08-07

2007-08-07

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S117000, C377S048000

Reexamination Certificate

active

11162160

ABSTRACT:
A clock frequency divider circuit and method of dividing a clock frequency are provided. The clock frequency divider circuit includes a first flip-flop circuit, a second flip-flop circuit, a third flip-flop circuit, a first logic control unit and a second logic control unit, wherein the first flip-flop circuit has two clock input terminals connected to the second and third flip-flop circuits respectively and two control signal input terminals connected to the first and second logic control units respectively. The second and third flip-flop circuits count rising edges and falling edges of an input frequency under control of the first and second flip-flop circuits and accordingly, symmetric output signals are output from the first flip-flop circuit.

REFERENCES:
patent: 4348640 (1982-09-01), Clendening
patent: 4866741 (1989-09-01), Minuhin
patent: 4951303 (1990-08-01), Larson
patent: 5764584 (1998-06-01), Fukiage et al.
patent: 6646465 (2003-11-01), Bal

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