Clock frequency divider circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control

Reexamination Certificate

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Details

C327S117000, C377S047000

Reexamination Certificate

active

11274256

ABSTRACT:
A clock frequency divider circuit including: a storing section for storing an input signal in synchronism with an input clock signal; a supplying section for supplying, as the input signal, one of a first value obtained by adding a value stored by the storing section to a numerator setting value and a second value obtained by subtracting a denominator setting value from the first value; a retaining section for retaining a most significant bit of the value stored by the storing section in synchronism with the input clock signal; and a logical product generating section for generating a logical product of a value retained by the retaining section and the input clock signal, and outputting the logical product as an output clock signal; wherein the supplying section supplies one of the first value and the second value as the input signal on a basis of the most significant bit of the value stored by the storing section.

REFERENCES:
patent: 4462110 (1984-07-01), Baldwin et al.
patent: 6445232 (2002-09-01), Logue et al.
patent: 6459309 (2002-10-01), Canard et al.
patent: 6618462 (2003-09-01), Ross et al.
patent: 2001-127618 (2001-05-01), None
Riley, T.A.D., Copeland, M.A., Kwasniewski, T.A.; “Delta-Sigma Modulation in Fractional-N Frequency Synthsis,” May 1993, IEEE Journal of Solid-State Circuits, vol. 28, Issue 5, pp. 553-559.

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