Clock feedthrough reduction system for switched current memory c

Details Clock feedthrough reduction system for switched current memory c Clock feedthrough reduction system for switched current memory c

1996-09-16

1998-07-21

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 91, G11C 2702, G05F 316

Patent

active

057839522

ABSTRACT:
A current cell for switch current circuits includes first and second MOS transistors connected in series between a constant current source and a reference ground. The first MOS transistor has its drain coupled to the constant current source and the second MOS transistor has its source coupled to the reference ground. Each of the two MOS transistors has a respective first and second switch coupling its control gate to its drain. The sample phase of a sample and hold operation is broken down into a first and second sample sub-phase, and an input current is applied to the current cell during both sample sub-phases. During the first sample sub-phase, the second MOS transistor memorizes a gate voltage corresponding to the input current, constant current source current and a clock feedthrough error. A channel effect is purposely induced in the second MOS transistor to a degree sufficient to compensate for, and correct, its clock feedthrough error. A modulation voltage is induced at the drain of the second transistor as a result of the channel effect, and the first MOS transistor is used to store and maintain this modulation voltage at the drain of the second MOS transistor during the hold phase.

REFERENCES:
patent: 4937469 (1990-06-01), Larson et al.
patent: 4958123 (1990-09-01), Hughes
patent: 5023489 (1991-06-01), Macbeth
patent: 5059832 (1991-10-01), Hughes
patent: 5109169 (1992-04-01), Hughes
patent: 5179301 (1993-01-01), Hughes
patent: 5296752 (1994-03-01), Groeneveld et al.
patent: 5349245 (1994-09-01), Hughes et al.
patent: 5666303 (1997-09-01), Hughes et al.
patent: 5714894 (1998-02-01), Redman-White et al.
Toumazou et al., "Regulated Cascode Switched-Current Memory Cell", Electronic Letters, vol. 26, No. 5, pp. 303-305, Mar. 1990.
Toumazou et al., "High-Performance Algorithmic Switch-Current Memory Cell", Electronics Letters, Sep. 1990, vol. 26, No. 19, pp. 1593-1595.
Hughes et al., "S.sup.2 I: A Switched-Current Technique for High Performance", Electronics Letters, Aug. 1993, vol. 29, No. 16, pp. 1400-1401.
Guggenbuhl et al., "Switched-Current Memory Circuits for High-Precision Applications", IEEE Journal of Solid-State circuits, Sep. 1994, vol. 29, No. 9, pp. 1108-1116.
Song et al., "A Clock Feedthrough Reduction Circuit for Switched-Current Systems", IEEE Journal of Solid-State Circuits, Feb. 1993, vol. 28, No. 2, pp. 133-137.
Groeneveld et al., "A Self-Calibration Technique for Monolithic High-Resolution D/A Converters", IEEE Journal of Solid-State Circuits, Dec. 1989, vol. 24, No. 6, pp. 1517-1522.
Helfenstein et al., "Clockfeedthrough Compensation Technique for Switched-Current Circuits", IEEE Transactions on Circuits and Systems, Mar. 1995, vol. 42, No. 3, pp. 229-231.

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