Clock fault detection circuit

Details Clock fault detection circuit Clock fault detection circuit

1994-04-05

1995-11-28

Beausoliel, Jr., Robert W.

Excavating

371 62, 307409, 307413, 327 44, 327291, 327292, 327298, 327299, G11B 2700, H03M 1300, H04L 700

Patent

active

054714885

ABSTRACT:
An apparatus for transferring data between a main processor and its memory and a packet switch includes a first bus coupled to the main processor and its memory, a bidirectional first-in-first-out (FIFO) buffer coupled between the first bus and a second bus, and having a first port connected to the first bus and a second port connected to the second bus, a communications processor, coupled to the second bus, a memory operatively coupled to the second bus, a first direct memory access (DMA) engine coupled between the first bus and the FIFO buffer for transferring data between the main processor and the FIFO buffer, a second direct memory access (DMA) engine coupled between the FIFO buffer and the second bus for transferring data between the FIFO buffer and the second bus, and a packet switch interface, operatively coupled between the second bus and the switch, for interfacing the second bus to the switch, wherein packets are communicated between the memory of the main processor and the switch in accordance with the communication protocol, and wherein the first and second DMA engines transfer data for the packets independently of each other.

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