Clock error detection circuit

Details Clock error detection circuit Clock error detection circuit

1996-06-06

1999-07-27

Tu, Trinh L.

Excavating

395558, 327 47, G06F 1100, G06F 922

Patent

active

059302755

ABSTRACT:
A method and digital circuit for indicating whether the frequencies of two clocks are within a predetermined range of each other, wherein a first pattern of alternating binary one's and zero's is created using the active edge of the first clock; first and second sampled patterns are generated by sampling the first pattern with respective first and second edges of the second clock; and a first acceptance signal is asserted if either the first or second sampled pattern has alternating binary one's and zero's. A second acceptance signal is asserted as above but interchanging the two clock signals. A near-frequency signal is generated when both acceptance signals are asserted. A clock error signal is the inversion of the near-frequency signal.

REFERENCES:
patent: 4777448 (1988-10-01), Satoh
patent: 5223833 (1993-06-01), Akata
patent: 5475322 (1995-12-01), MacDonald
patent: 5663970 (1997-09-01), Bae
patent: 5670901 (1997-09-01), Yoshida

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