Clock error detection apparatus and method

Details Clock error detection apparatus and method Clock error detection apparatus and method

2011-04-19

2011-04-19

Kim, Kevin Y (Department: 2611)

Pulse or digital communications

Receivers

Automatic frequency control

Reexamination Certificate

active

07929648

ABSTRACT:
An error detection apparatus and method compares a first hardwired value such as a first clock threshold, and a second hardwired value such as a second clock threshold, and generates an indication that there is an error in a clock signal based on a comparison of the first hardwired value and the second hardwired value to the clock signal. If an error is detected, the error detection apparatus will, for example, interrupt clock recovery logic to take proper action for recovery of a clock generation circuit that generated the clock signal. The clock signal may be generated based on, for example, a reference clock signal that may be provided by an external source clock, or any other suitable source.

REFERENCES:
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patent: 6433599 (2002-08-01), Friedrich et al.
patent: 6993104 (2006-01-01), Morgan et al.
patent: 2006/0212247 (2006-09-01), Shimoyama et al.
patent: 2007/0153949 (2007-07-01), Chen et al.

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