Clock-edge modulated serial link with DC-balance control

Details Clock-edge modulated serial link with DC-balance control Clock-edge modulated serial link with DC-balance control

2005-10-31

2009-12-01

Ahn, Sam K (Department: 2611)

Pulse or digital communications

Cable systems and components

Reexamination Certificate

active

07627044

ABSTRACT:
A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.

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Kyeongho Lee, et al., “1.04 GBd Low EMI Digital Video Interface System Using Small Serial Link Technique,”IEEE Journal of Solid-State Circuits, vol. 33, No. 5, May 1998, pp. 816-823.
Wei-Hung Chen, et al., “A CMOS 400-Mb/s Serial Link for AS-Memory Systems Using a PWM Scheme,”IEEE Journal of Solid-State Circuits, vol. 36, No. 10, Oct. 2001, pp. 1498-1505.

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