Clock duty cycle control technique

Details Clock duty cycle control technique Clock duty cycle control technique

1998-06-30

2000-07-04

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

327155, 327163, 327292, H03K 3017

Patent

active

060844523

ABSTRACT:
An apparatus adjusts the duty cycle of a single-ended clock signal. The single-ended clock signal oscillates between first and second voltages. The apparatus includes an error indication circuit, a duty cycle error measurement circuit and a duty cycle adjuster. The error indication circuit includes a reference circuit and a comparison circuit. The reference circuit is coupled to a first node having the first voltage and a second node having the second voltage to generate a reference signal from the first and second voltages. The reference circuit includes at least one instance of a first electrical characteristic cell. The comparison circuit is coupled to receive a feedback clock signal and to generate a comparison signal therefrom. The comparison circuit includes at least one instance of the first electrical characteristic cell. The duty cycle error measurement circuit is coupled to receive the reference signal and the comparison signal. The duty cycle error measurement circuit rejects the common mode of the reference and comparison signals and passes the differential mode of the reference and comparison signals to generate a duty cycle adjust signal responsive to receiving the reference and comparison signals. The duty cycle adjuster is coupled to receive an input clock signal and the duty cycle adjust signal and to provide the single-ended clock signal. The single-ended clock signal has a duty cycle determined at least in part by the duty cycle adjust signal.

REFERENCES:
patent: 4460985 (1984-07-01), Hoffman
patent: 4527075 (1985-07-01), Zbinden
patent: 5053639 (1991-10-01), Taylor
patent: 5057702 (1991-10-01), Kitagawa
patent: 5231320 (1993-07-01), Kase
patent: 5315164 (1994-05-01), Broughton
patent: 5422529 (1995-06-01), Lee
patent: 5477180 (1995-12-01), Chen
patent: 5572158 (1996-11-01), Lee et al.
patent: 5614855 (1997-03-01), Lee et al.
Stefanos Sidiropoulos and Mark Horowitz, "A 700-Mb/s/pin CMOS Signaling Interface Using Current Integrating Receivers," IEEE Journal of Solid-State Circuits, May 1997, vol. 32, No. 5, pp. 681-690.
Thomas H. Lee et al, FA 18.6: A 2.5V Delay-Locked Loop for an 18Mb 500MB/s DRAM, IEEE International Solid-State Circuits Conference, High-Performance Logic and Circuit Techniques, Feb. 18, 1994, pp. 300-301.
Alex Waizman, "FA 18.5: A Delay Line Loop for Frequencey Synthesis of De-Skewed Clock," IEEE International Solid-State Circuits Conference, High Performance Logic and Circuit Techniques, Feb. 18, 1994, pp. 289-299.

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