Clock driver circuit and semiconductor integrated circuit device

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating

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Details

327565, 327566, 324769, 324765, 324527, 324201, H01L 2352, H01L 2710

Patent

active

059146257

ABSTRACT:
A clock driver circuit comprises a first and a second clock driver 15a and 15b. In each of these clock drivers, a plurality of main drivers 19(1) through 19(n) have their input nodes and output nodes connected respectively to a first and a second common line 18 and 21. The second common line 21 is connected to a plurality of clock signal supply lines 20(1) through 20(m) which in turn are connected to the clock input nodes of second macro cells 16 each requiring a clock signal. In a test mode, the first and second common lines 18a and 21a of the first clock driver 15a and the first and second common lines 18b and 21b of the second clock driver 15b are electrically connected by first and second connection means 22 and 24, respectively. Thus, a clock driver circuit is provided that offers high driving ability with negligible clock skews in both normal mode and test mode.

REFERENCES:
patent: 4883980 (1989-11-01), Morimoto
patent: 5254886 (1993-10-01), El-Ayat
patent: 5444276 (1995-08-01), Yokota

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