Clock driver circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating

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Details

327200, 327201, 327395, 327400, 327407, 327415, G06F 104

Patent

active

055962963

ABSTRACT:
A clock driver circuit comprises a first driver including first and second inverters cascaded between an input terminal and a first output terminal for outputting a non-inverted signal delayed from the clock signal applied to the input terminal by a delay amount corresponding to two stages of inverters. The clock driver circuit also comprises and a second driver including third, fourth and fifth inverters cascaded between the input terminal and a second output terminal and a sixth inverter connected between the input terminal and the second output terminal. With this arrangement, a first signal delayed from the clock signal applied to the input terminal by a first delay amount corresponding to the third, fourth and fifth inverters, is synthesized by a wired-OR at the second output terminal with a second signal delayed from the clock signal applied to the input terminal by a second delay amount corresponding to the sixth inverter. Thus, a synthesized inverted signal delayed from the clock signal applied to the input terminal by a delay amount corresponding to two stages of inverters, is outputted from the second output terminal.

REFERENCES:
patent: 4154978 (1979-05-01), Tu
patent: 5434525 (1995-07-01), Leonowich
Japan Society of Electronics, Information and Communication, Spring Meeting Transactions, 1992, C-565, p. 186.

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