Clock driver circuit

Details Clock driver circuit Clock driver circuit

1985-12-17

1987-02-24

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307262, 307601, 307605, 328 55, 328 62, 328 63, 377105, H03K 513

Patent

active

046459472

ABSTRACT:
A driver circuit for generating non-overlapping clocking signals. A single clocking source is divided down into two clock signals which are passed through a plurality of inverter delay chains to insure non-overlapping output signals. Inverters made up of CMOS transistors having long channel lengths are utilized in order to eliminate overlap between the clock signals. Inverter delay chains are also utilized to prevent skewing between a true clock output signal and its complement.

REFERENCES:
patent: 3996478 (1976-12-01), Kasperkovitz
patent: 4140927 (1979-02-01), Feucht
patent: 4394586 (1983-07-01), Morozumi
patent: 4456837 (1984-06-01), Schade, Jr.
patent: 4472645 (1984-09-01), White

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