Clock doubler

Details Clock doubler Clock doubler

2006-06-13

2006-06-13

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S116000, C327S119000, C327S120000, C327S121000

Reexamination Certificate

active

07061285

ABSTRACT:
A clock doubler including clock doubling circuitry for generating from a system clock a clock signal having a frequency substantially double that of the system clock and also having a pulse width and associated duty cycle is provided. Timing circuitry for generating a first signal indicative of the time the clock signal is low and a second signal indicative of the time the clock signal is high provides an input to comparison circuitry for comparing the first signal and the second signal. Pulse width varying circuitry varies the pulse width of the clock signal based on the result of comparing the first signal and the second signal.

REFERENCES:
patent: 5963071 (1999-10-01), Dowlatabadi
patent: 5994930 (1999-11-01), Park
patent: 6091271 (2000-07-01), Pant et al.
patent: 6094076 (2000-07-01), Saeki
patent: 6380774 (2002-04-01), Saeki
patent: 6441657 (2002-08-01), Saeki
patent: 6545518 (2003-04-01), Saeki
patent: 2001/0056332 (2001-12-01), Abrosimov et al.
patent: 2003/0007162 (2003-01-01), Blumer

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