Clock divider with bypass and stop clock

Details Clock divider with bypass and stop clock Clock divider with bypass and stop clock

2001-10-11

2002-11-19

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C327S115000, C327S117000, C327S159000, C327S415000

Reexamination Certificate

active

06483888

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to circuits for generating and controlling computer clocks and in particular to circuits for selecting clock signals.
BACKGROUND INFORMATION
Phase-locked loops (PLL's) have been widely used in high-speed communication systems because PLL's efficiently perform clock recovery or clock generation at a relatively low cost. Dynamic voltage and frequency scaling is a critical capability in reducing power consumption of power sensitive devices. Scaling, in this sense, means the ability to select high performance with a nominal power supply voltage and a high frequency clock operation or low performance by reducing the power supply voltage and the corresponding clock frequency. Reducing the system power is usually done when performance is not needed or when running from a limited energy source such as a battery. To allow low power operation, the PLL and other circuits must support very aggressive power/energy management techniques. For the PLL this means low power operation while supporting key required features such as dynamic frequency scaling, dynamic voltage scaling, clock freezing and alternate low frequency clocking. Dynamic implies that the PLL is able to support changes in the output frequency and logic supply voltage without requiring the system to stop operation or waiting for the PLL clock to reacquire lock.
Using a PLL or delay-locked loop (DLL) has advantages in a battery powered system because a PLL is able to receive a lower frequency reference frequency from a stable oscillator to generate system clock frequencies. A PLL also allows changing the system clock frequency without changing the reference frequency.
In switching between two or more clocks in a PLL or other logic system it may be important for the switching to be glitch-free. For example, transients that occur on a clock in a computer system may be mistaken by the logic system as a valid clock edge and thus create timing problems or system failures. In a system employing frequency scaling, it is desirable to select between a high frequency clock, and a divided lower frequency clock, and stopping either selected clock and restarting with the selected clock in a glitch-free circuit.
There is, therefore, a need for a circuit for selecting between two synchronous clocks while incorporating a mode for stopping either clock in a known state and restarting a stopped clock on a known transition while assuring glitch-free switching.
SUMMARY OF THE INVENTION
A multiplexer (MUX) receives a high frequency clock and a low frequency clock divided from the high frequency clock. A latch circuit receives a Bypass signal which selects one of the clocks. The state of the Bypass signal is latched in a first latch when the output of the MUX transitions to a logic one. A second latch circuit receives the output of the first latch and latches the state of its output when the MUX output transitions to a logic zero. A third latch circuit receives the output of the second latch and latches the state of its output when both the high frequency and low frequency clock are concurrently at a low level. The output of the third latch is the MUX control signal that selects either the high frequency or a low frequency clock while guaranteeing that a cycle with a new clock begins on the first positive logic transition following a state when both clocks are at a logic zero. The output of the MUX is coupled to a logic AND gate that is gated with a latched Freeze clock signal that determines whether the clock output signal is active or is held at a logic zero state. The state of a Freeze clock signal is latched in a fourth latch when the MUX output transitions to a logic one. A fifth latch latches the output of the fourth latch when the MUX output transitions to a logic zero guaranteeing that the MUX output is selected as the clock output signal when the MUX output is a logic zero (starts on the next transition to a logic one) or that the clock is “frozen” low when the clock output signal is at a logic zero, resulting in no glitches. The clock output signal is stopped when it is low and re-started when the MUX output is a logic zero assuring that the clock output signal is glitch-free during switching of the MUX or when a clock output signal is stopped or started.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


REFERENCES:
patent: 6201448 (2001-03-01), Tam et al.

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