Clock divider for analysis of all clock edges

Details Clock divider for analysis of all clock edges Clock divider for analysis of all clock edges

2001-07-31

2002-08-27

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S117000, C327S166000, C327S235000, C377S047000, C708S103000, C331S051000

Reexamination Certificate

active

06441656

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The invention relates generally to a micro-electronic clock system. More specifically, the invention relates to a clock divider that allows for analysis of all of the clock edges.
2. Background Art
A clock signal is critical to the operation of a microprocessor based computer system. The clock signal initiates and synchronizes the operation of almost all of the components of such a computer system. Consequently, the detection of any errors or problems with the clock signal is vitally important.
A phased locked loop (PLL) is an important part of a clock signal distribution system. A PLL is a component that uses feedback to maintain an output signal in a specific phase or frequency relationship with an input signal. In the case of a computer system, a PLL is used to synchronize the microprocessor (“chip”) clock with the external (“system”) clock. Such synchronization is necessary because a chip clock typically operates at a much greater frequency than the system clock. Consequently, the PLL operates at the same higher frequency because it serves the chip clock.
FIG. 1
shows a prior art overview of a clock distribution system. The computer system
10
broadly includes an input/output (“IO”) ring
12
that is external to the microprocessor chip or “core”
14
of the system. The system clock signal
16
is fed through the IO ring
12
to the PLL
15
inside the core
14
. The PLL
15
, after synchronizing the system clock signal with the chip clock signal, feeds it
to a global clocking grid
18
for the chip. The global clocking grid
18
feeds the signal data/scan paths and various components such as system latches
22
, local clocking grids
20
, and a feed back loop
26
that returns to the PLL
15
. The local clocking grids
20
feed the base components of the core
14
such as flip-flops
24
which as basic data storage devices.
The PLL clock signal
28
is also sampled after the PLL
15
in order to analyze the signal performance off chip. Specifically, the PLL signal
28
is checked for the effects of system noise (called “jitter”) and timing errors (called “skew”). However, difficulties arise in trying to observe the PLL signal
28
because it is often operating at frequencies up to 3 GHz. The off-chip drivers that drive the signal
28
generally cannot support this speed because they operate at lower frequencies. While a few clock edges might be observed, the higher frequency energy that causes the problems that are trying to be detected will be filtered out. A solution is needed that allows for observation and analysis of all the clock edges.
SUMMARY OF INVENTION
In some aspects, the invention relates to a method for dividing a clock signal into multiple phases, comprising: inputting the clock signal to a clock divider segment group, wherein the clock divider segment group comprises at least one clock divider segment; generating a first half of the multiple phases with the clock divider segment group; and generating a second half of the multiple phases with an inverse output from the clock divider segment group.
In other aspects, the invention relates to a method for dividing a clock signal, comprising: inputting the clock signal to a divider; generating a first phase of the clock signal with the divider; generating a second phase of the clock signal with the divider, wherein the second phase lags behind the first phase by one clock cycle; generating a third phase of the clock signal by inverting the first phase; and generating a fourth phase of the clock signal by inverting the second phase.
In other aspects, the invention relates to an apparatus for dividing a clock signal, comprising: a means for inputting the clock signal to a divider; means for generating multiple initial phases of the clock signal with the divider; and means for generating an multiple additional phases of the clock signal by inverting corresponding initial phases of the clock signal.
In other aspects, the invention relates to an apparatus for dividing a clock signal, comprising: a divider input that receives the clock signal; a first phase generator that generates a first phase of the clock signal; a second phase generator that generates a second phase of the clock signal, wherein the second phase lags behind the first phase by one clock cycle; a third phase generator that generates a third phase of the clock signal by inverting the first phase; and a fourth phase generator that generates a fourth phase of the clock signal by inverting the second phase.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 5574756 (1996-11-01), Jeong
patent: 5781054 (1998-07-01), Lee
patent: 6194939 (2001-02-01), Omas
patent: 6316982 (2001-11-01), Gutierrez, Jr.

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