Clock divider circuit

Details Clock divider circuit Clock divider circuit

2005-02-15

2005-02-15

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S115000, C377S048000

Reexamination Certificate

active

06856184

ABSTRACT:
A system that includes a first circuit configured generate a first set of encoded signals in response to a first clock signal and a second circuit configured to generate a second set of encoded signals in response to the first clock signal is provided. The system also includes a third circuit configured to generate a first pulse signal and a second pulse signal in response to the first set of encoded signals and the second set of encoded signals, and a fourth circuit configured to generate a second clock signal in response to the first pulse signal and the second pulse signal.

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SFF Committee “Information Specification for SFP (Small Formfactor Pluggable) Transceiver”, SFF-8074i, Rev. 1.0, pps. 1-38 (May 12, 2001), <ftp://ftp.seagate.com/sff>.
SFF Committee “Specification for Diagnostic Monitoring Interface for Optical Xcvrs”, SFF-8472, Rev. 9.3, pps. 1-10 and 1-29, (Aug. 1, 2002), <ftp://ftp.seagate.com/sff>.

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