Clock divider and method for dividing a clock signal in a...

Details Clock divider and method for dividing a clock signal in a... Clock divider and method for dividing a clock signal in a...

2002-12-30

2004-11-09

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S117000

Reexamination Certificate

active

06815985

ABSTRACT:

TECHNICAL FIELD
A clock divider and a method for dividing a clock signal in a DLL circuit of a semiconductor memory device are disclosed.
DESCRIPTION OF THE RELATED ART
Generally, clock signals are used as reference signals to set operation timing in a system or a circuit, and to ensure high-speed operation of the system or circuit without any errors. When a clock signal from an external circuit is used internally within a circuit, a time delay, i.e., a clock skew may be generated due to the internal circuit. A delay locked loop (DLL) circuit may be used to ensure that the internal clock signal of the circuit has the same phase as the external clock signal by compensating for the clock skew.
Important characteristics of a DLL circuit include small size, low jitter, and fast locking time. These characteristics may require semiconductor memory devices of the future, which may also require low power consumption and high-speed operation. A DLL circuit is less influenced by noise than a phase locked loop (PLL) circuit. As a result, a DLL circuit may be used in a synchronous semiconductor memory device, such as, for example, a DDR SDRAM (double data rate synchronous DRAM) or the like. A DLL circuit of a register type is frequently used in many kinds of DLL circuits.
FIG. 1
is a block diagram illustrating a conventional resister-control-type DLL circuit of a typical DDR SDRAM.
The conventional register-control-type DLL circuit of the typical DDR SDRAM includes a clock buffer
110
, a first clock divider
130
, a delay circuit
150
, a clock multiplexer
170
, a second clock divider
190
, a delay model
210
, a phase comparator
230
, and a delay controller
250
.
The clock buffer
110
converts a voltage level of a high frequency external clock signal CLK and a high frequency external clock inversion signal CLKB, both of which are supplied from an external circuit, into a power supply voltage level VDD. The first clock divider
130
outputs a low frequency reference clock signal by dividing a high frequency clock signal CLKD of a VDD level by n, wherein n is a positive integer, (e.g., n is 4). The delay circuit
150
delays the high frequency clock signal CLKD of the VDD level a predetermined delay amount and outputs a delayed clock signal to the clock multiplexer
170
. The delay circuit
150
includes a plurality of delay units forming a delay chain and a shift register for controlling the plurality of delay units. Each delay unit includes a NAND gate and an inverter. The clock multiplexer
170
outputs the delayed clock signal OUTPUT DLL_CLK to an external circuit and to the second clock divider
190
. The second clock divider
190
divides the delayed clock signal from the clock multiplexer
170
by n, wherein n is a positive integer (e.g., n is 4). The delay model
210
is configured so that a feedback signal has an identical delay condition as the real clock signal path.
The phase comparator
230
compares the phase of the internal feedback signal outputted from the delay model
210
with the phase of the reference clock signal REF. The delay controller
250
outputs shift control signals SR and SL for controlling a shift direction of the shift register in the delayed circuit
150
and a delay locking signal representing that delay locking is achieved in response to control signals EARLY and LATE outputted from the phase comparator
230
.
The delay model
210
, also called a replica circuit, includes a dummy clock buffer, a dummy output buffer, and a dummy load. A delay time of the delay model
210
is generated that is identical to a delay time generated in the real clock signal path. Because of the delay circuit
150
, the delay controller
250
, and the phase comparator
230
delay the external clock signal CLK a desired delay amount, they are called a delay unit.
Because the delay model
210
includes a dummy clock buffer, a dummy output buffer and a dummy load, a delay time of the clock signal generated from the delay model
210
can be compensated. At this time, since the external clock signal is not synchronized with the internal clock signal, the delay operation for synchronizing the external clock signal with the internal clock signal is repeated in the delay circuit
150
. Since the delay amount of the delay model
210
cannot be changed to achieve locking, the total delay amount has to be adjusted in the delay circuit
150
. A condition for achieving locking is as follows:
 
DD+RR=
n
T
  (Eq. 1)
Where, DD is a delay amount of the delay circuit
150
, RR is a delay amount of the delay model
210
, T is a period of the external clock signal, and n is an integer, e.g., 1 or 2.
DD=n
T−RR  (Eq. 2)
Accordingly, an output DLL clock signal OUTPUT_DLL_CLK is provided by repeatedly delaying the high frequency clock signal CLKD by as much as DD, which is the delay amount that is repeatedly adjusted in the delay circuit
150
. Additionally, a negative delay that precedes the external clock signal by as much as RR may be achieved in the DLL circuit.
FIG. 2A
is a timing diagram illustrating one period (1T) based dividing of a clock signal capable of being used in a low frequency band.
FIG. 2B
is a timing diagram illustrating two periods (2T) based dividing of a clock signal capable of being used in a high frequency band.
Referring to
FIG. 2A
, since a rising edge of the feedback clock signal, which is compared to the reference clock signal REF in the phase comparator
230
in the low frequency band, is before the rising edge of the reference clock signal REF, locking can be achieved by repeatedly increasing the delay amount in the delay circuit
150
. In this case, because the pulse width of the divided reference clock signal REF corresponds to one period of the external clock signal CLK, it is called one-period-based dividing or 1T-based dividing.
Referring to
FIG. 2B
, since a rising edge of the feedback clock signal, which is compared to the reference clock signal REF in the phase comparator
230
in the high frequency band, is before the rising edge of the reference clock signal REF, locking can be achieved by repeatedly increasing the delay amount in the delay circuit
150
. Accordingly, because the pulse width of the divided reference clock signal REF corresponds to two periods of the external clock signal CLK, locking can be achieved. Additionally, because the pulse width of the divided reference clock signal REF corresponds to two periods of the external clock signal CLK, it is called two-periods-based dividing or 2T-based dividing.
FIG. 3A
is a circuit diagram illustrating a conventional four-dividing circuit for one-period-based dividing of a clock signal in which the pulse width of the divided reference clock signal REF is not adjustable. The four-dividing circuit may be located in the clock dividers, e.g. the the first clock divider
130
and the second clock divider
190
, according to the prior art.
FIG. 3B
is a timing diagram showing the operation of the conventional four-dividing circuit of FIG.
3
A.
If the clock signal CLKD from the clock buffer
110
is provided as an input to the first dividing unit
310
in response to a DLL enable signal DLL_ENABLE, the clock signal CLKD is divided by two and a two-divided clock signal DIVIDE_
2
is outputted. Thereafter, if the two-divided clock signal DIVIDE_
2
is provided as an input to a second dividing unit
330
, the two-divided clock signal is divided again by two and a four-divided clock signal DIVIDE_
4
is outputted. The four-divided clock signal is maintained in a high state for one period of the externally supplied clock signal CLKD and then is maintained in a low state.
FIG. 4A
is a circuit diagram illustrating a conventional four-dividing circuit for one-period-based dividing in which the pulse width of the divided reference clock signal REF is adjustable. The four-dividing circuit may be located in the clock dividers, e.g., the first clock divider
130
and the second clock divider
190
, according to the prior art.
FIG. 4B
is a timing diagram sho

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