Clock distribution system for reducing clock skew between proces

Details Clock distribution system for reducing clock skew between proces Clock distribution system for reducing clock skew between proces

1992-11-02

1996-03-26

Harrell, Robert B.

Boots, shoes, and leggings

364DIG1, 364DIG2, 364270, 3642705, 364271, G06F 1300

Patent

active

055028195

ABSTRACT:
A clock distribution system for reducing clock skew between tightly coupled central processing units in a multi-processor system. The multi-processor system includes (1) a configuration processor for generating a first configuration signal and a second configuration signal, a first clock, a second clock, (2) a first processor having a first central processing unit, (3) a second processor having a second central processing unit, (4) a first clock generator for generating a first delayed clock signal from the first or second clock in accordance with the configuration signals, and (6) a second clock generator generating a second delayed clock signal from the first or second clock in accordance with said configuration signals. The clock distribution system comprises a distribution means for receiving the first delayed clock signal, the second delayed clock signal and the configuration signals, and for distributing in accordance with the configuration signals either the first delayed clock to the first central processing unit and the second delayed clock to the second central processing unit, or the first delayed clock signal to both the first and second central processing unit or the second delayed clock signal to both the first and second central processing unit.

REFERENCES:
patent: 4696019 (1987-09-01), Tulpule et al.

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