Clock distribution system for automatic test equipment

Details Clock distribution system for automatic test equipment Clock distribution system for automatic test equipment

2003-06-12

2004-11-23

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S293000, C327S295000

Reexamination Certificate

active

06822498

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to automatic test equipment, and more specifically to clock distribution systems for automatic test equipment.
BACKGROUND OF THE INVENTION
Automatic test equipment enables semiconductor device manufactures to test newly fabricated devices in a manufacturing setting. The equipment typically drives test signals to and receives response signals from a device-under-test. The response signals are then compared to expected signals to determine if the device passed or failed the test.
Like the semiconductor devices they test, automatic test equipment involves a high degree of sophisticated circuitry. The circuitry is typically employed in the form of integrated circuits that define “channels” for the automatic test equipment, or tester. Generally, each channel is controlled by a clock in the tester. For each period of the tester clock, each channel can generate or measure the signal. Consequently, the quality, or accuracy of the tester clock plays an important role in the ability of the tester to identify passing or failing devices.
As device speeds increase, the tester clocks also typically increase. Whereas conventional test signals on the order of less than one gigahertz could successfully be distributed to the channel circuitry over long distances, higher frequency signals on the order of one or more gigahertz tend to attenuate even over relatively short distances.
One potential solution to preserve the clock integrity is to distribute the clock as a differential digital signal to the tester channel IC's. Unfortunately, at 800 megahertz and beyond, standard differential signals drift apart over three-hundred centimeters, and are no longer differential at the destination. Moreover, the digital circuitry typically employed to generate and drive the differential clock often produces undesirable distortion that affects the accuracy of the signal. Another problem with this approach is that if the source signal includes noise components, there is no common-mode rejection of the source noise.
Another possible solution is to avoid the differential approach and instead drive a single-ended signal along the fanout transmission line. However, single-ended signals are susceptible to locally generated and ASIC generated common mode noise.
What is needed and currently unavailable is a clock distribution system that allows for relatively long fanout lengths while maintaining optimal clock signal integrity. The clock distribution system of the present invention satisfies these needs.
SUMMARY OF THE INVENTION
The clock distribution system of the present invention provides a unique way of fanning out a high frequency clock signal to a plurality of integrated circuits with minimal distortion. In addition, the invention advantageously provides simultaneous rejection of locally generated common-mode noise. By providing a relatively distortion-free clock signal, higher accuracy in the integrated circuit timings are realized.
To realize the foregoing advantages, the invention in one form comprises a clock system for providing a high-speed clock signal to a plurality of integrated circuits. The clock system includes an analog signal generator for producing a periodic analog signal of a predetermined frequency and fanout circuitry. The fanout circuitry is coupled to the analog signal generator and includes a transmission line and an RF coupler. The system further includes a plurality of receivers. Each receiver has reference signal input circuitry and clock signal input circuitry. Both the reference signal circuitry and the clock signal circuitry are receptive to coupling locally generated common mode noise. The clock signal circuitry is disposed proximate the RF coupler to provide an RF coupling therebetween.
In another form, the invention comprises a clock system for providing a high-speed clock signal to a plurality of integrated circuits. The clock system includes means for producing a periodic analog signal of a predetermined frequency and means for fanning out the periodic analog signal. The system further includes a plurality of receivers. Each receiver has means for receiving a reference input signal and means for receiving a clock input signal. Both the means for receiving a reference input signal and the means for receiving a clock input signal are receptive to coupling locally generated common mode noise. The system additionally includes means for RF coupling the periodic analog signal to the means for receiving a clock input signal.
In a further form, the invention comprises a method of distributing a high-frequency clock signal to a plurality of receivers. Each receiver has a clock input and a reference input. The method includes the steps: driving a single-ended analog periodic signal along a transmission line path; RF-coupling the single-ended signal to the clock input at a point proximate the clock input; and mutually coupling locally generated common-mode noise between the reference input and the clock input.
Other features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.


REFERENCES:
patent: 5293626 (1994-03-01), Priest et al.
patent: 6098176 (2000-08-01), Coteus et al.
patent: 6294933 (2001-09-01), Chun et al.
patent: 6433605 (2002-08-01), Zhang
patent: 6452442 (2002-09-01), Laude

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