Clock distribution system and technique

Pulse or digital communications – Repeaters – Testing

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Details

375107, H04L 2728, H04L 512

Patent

active

050581325

ABSTRACT:
A clock distribution device (CDD) (100) is used in a concentrator (200,300) to distribute multiple bits of serial data (208) in parallel across back plane boards (Board A, B, N. NN) as a byte-wide data signal (214). Each back plane board (Board A, B, N, NN) has a CDD (100). One back plane board (Board A) has a master oscillator (120) which generates a local low frequency reference clock signal (212). The reference clock signal (212) is distributed to all of the back plane boards (Board A, B, N, NN) where each board's CDD (100) uses the reference clock signal (212) to generate a high frequency clock signal (TXCLK) and a plurality of local phase separated clock signals (LBC1-LBC5). Each board has a receiver (156a) and a transmitter (156b) and the low frequency clock signals (LBC1-LBC5) are employed to synchronize and deskew the parallel data signal (214) transmitted across the back plane from board to board by using the local phase separated clock signals (LBC1-LBC5) generated on each board to strobe out the serial data (208) from the receiver (156a) in parallel as the parallel data signal (214), to latch in the parallel data signal (214) into a latch (LATCH) internal to the transmitter (156b), to enable a storage register (TXSR) on the transmitter (156b) which stores the parallel data signal (214) for conversion back to serial data, and to strobe in the parallel data signal (214) into a latch (170) when the CDD (100) is used in a large concentrator (300).

REFERENCES:
patent: 4646324 (1987-02-01), Albano et al.
Floyd E. Ross, "FDDI-An Overview"; Digest of Papers, Computer Soc. Intl. Conf. Compcon '87, pp. 434-444.
FDDI Physical Layer Medium Dependent (PMD), Draft Proposal American National Standard, X3T9, 5/84-49, Rev. Jul. 1, 1988.
The Supernet Family for FDDI, Databook, Advanced Micro Devices, 1/1-6/17, 1989.

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