Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock
Patent
1992-06-24
1994-03-22
Callahan, Timothy P.
Electrical transmission or interconnection systems
Personnel safety or limit control features
Interlock
3074821, 361785, 361796, H05K 720
Patent
active
052967484
ABSTRACT:
A seamless clock distribution scheme for a system incorporating sequential digital logic devices disposed on multiple parallel boards for reducing or substantially eliminating skew. The multiple parallel boards are positioned on and project outward from one side of a centerplane. A single clock board, generating multiple copies of the system clock and mounted at a right angle to the parallel boards on the opposite side of the centerplane are connected by shared pins passing through apertures formed in the centerplane. This shared pin connection allows for simple, though near-ideal transmission of the clock signal copies between the parallel logic boards and the clock board with a minimum mismatch of the clock signal between two parallel boards.
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"To Clear System Bottlenecks Drive Backplanes with ECL" by Jim Mears, Electric Design, Oct. 15, 1987, pp. 83-88.
Mullaney John P.
Wicklund Denton G.
Callahan Timothy P.
Network Systems Corporation
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