Clock distribution scheme for user-programmable logic array arch

Details Clock distribution scheme for user-programmable logic array arch Clock distribution scheme for user-programmable logic array arch

1992-06-19

1993-10-19

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 3074651, 307480, 307243, H03K 19177

Patent

active

052548864

ABSTRACT:
A clock distribution architecture is disclosed for use in a user-programmable logic array integrated circuit comprising an array of user-programmable logic elements having inputs and outputs, at least some of the user-programmable logic elements including sequential logic elements having clock inputs, and further including a plurality of general interconnect lines which may be connected to one another and to the inputs and outputs of the logic elements. The clock distribution architecture includes at least one clock input pin on the integrated circuit, a plurality of clock distribution lines disposed in the array, at least one buffer amplifier having an input connected to the clock input pin and an output connected to at least one of the clock distribution lines. At least one inverter has an input connected to at least one of the clock distribution lines, and an output. A multiplexer is associated with each of the sequential logic elements, each of the multiplexers has a first input connected to one of the clock distribution lines, a second input connected to the output of the inverter, and a third input connected to a clock signal line connectable to at least one of the general interconnect line through a user-programmable element, an output connected to the clock input of the sequential element with which it is associated, and control inputs selecting which of the first, second, and third inputs is connected to the output.

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