Clock distribution providing optimal delay

Details Clock distribution providing optimal delay Clock distribution providing optimal delay

2006-08-01

2006-08-01

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S295000

Reexamination Certificate

active

07084688

ABSTRACT:
The invention provides a clock delay arrangement accounting for the worst-case delay situation of data signals, which is independent of the layout and technology. It comprises a main clock line; two dummy clock lines, each arranged parallel to the main clock line, and the main clock line disposed between the two dummy clock lines; and a clock source coupled to the main clock line and the two dummy clock lines, adapted to drive said dummy clock lines in phase opposition with respect to the main clock line.

REFERENCES:
patent: 5991229 (1999-11-01), Kim et al.
patent: 6211714 (2001-04-01), Jeong
patent: 6288589 (2001-09-01), Potter et al.

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