Clock distribution phase alignment technique

Details Clock distribution phase alignment technique Clock distribution phase alignment technique

2001-03-29

2003-10-07

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S291000, C327S293000, C327S297000, C327S292000

Reexamination Certificate

active

06630855

ABSTRACT:

FIELD
The present invention relates to a clock distribution phase alignment technique and more particularly to an active phase alignment technique utilizing a PLL (Phase Locked Loop).
BACKGROUND
At present, many integrated circuits, particularly large-scale integrated circuits, require a clock signal to be distributed to numerous locations throughout the integrated circuit die. Processors, such as microprocessors, are but one example of such large-scale integrated circuits requiring a clock signal to be distributed throughout the integrated circuit die.
In the past, the clock speeds of the clock signals in such integrated circuits were slow enough to such that the difference in phase (skew) between the clock signal at one point in the integrated circuit die and the clock signal at another point in the integrated circuit die was negligible.
Accordingly, as illustrated in
FIG. 1
, an integrated circuit die
100
included a clock signal generator
114
connected to a buffer amplifier
115
which was in turn connected to a clock distribution spine
110
. The left side of the die received the clock signal from the outputs of buffer amplifiers
120
,
121
,
122
, and
123
while the right side of the die received the clock signal from the outputs of buffer amplifiers
124
,
125
,
126
, and
127
.
However, with the advent of integrated circuits having extremely high clock speeds (into the GHz range), it has been found that the single clock distribution arrangement as illustrated in
FIG. 1
is unsuitable in view of the fact that the skew between the clock signal at one point in the integrated circuit die is no longer negligible with respect to the clock signal at another point in the integrated circuit die.


REFERENCES:
patent: 5420544 (1995-05-01), Ishibashi
patent: 5465347 (1995-11-01), Chao et al.
patent: 5880612 (1999-03-01), Kim
patent: 5949262 (1999-09-01), Dreps et al.
patent: 6075832 (2000-06-01), Geannopoulos et al.

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