Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2007-02-06
2007-02-06
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S698000, C257S737000
Reexamination Certificate
active
11131711
ABSTRACT:
A clock distribution network (110) is formed on a semiconductor interposer (320) which is a semiconductor integrated circuit. An input terminal (120) of the clock distribution network is formed on one side of the interposer, and output terminals (130) of the clock distribution network are formed on the opposite side of the interposer. The interposer has a through hole (360), and the clock distribution network includes a conductive feature going through the through hole. The side of the interposer which has the output terminals (130) is bonded to a second integrated circuit (310) containing circuitry clocked by the clock distribution network. The other side of the interposer is bonded to a third integrated circuit or a wiring substrate (330). The interposer contains a ground structure, or ground structures (390, 510), that shield circuitry from the clock distribution network. Conductive lines (150) in an integrated circuit are formed in trenches (610) in a semiconductor substrate.
REFERENCES:
patent: 5001525 (1991-03-01), Kenney
patent: 5057895 (1991-10-01), Beasom
patent: 5119155 (1992-06-01), Hieda et al.
patent: 5177594 (1993-01-01), Chance et al.
patent: 5251097 (1993-10-01), Simmons et al.
patent: 5416861 (1995-05-01), Koh et al.
patent: 5466963 (1995-11-01), Beasom
patent: 5501006 (1996-03-01), Gehman, Jr. et al.
patent: 5665989 (1997-09-01), Dangelo
patent: 5761350 (1998-06-01), Koh
patent: 5811868 (1998-09-01), Bertin et al.
patent: 5933717 (1999-08-01), Hause et al.
patent: 6037822 (2000-03-01), Rao et al.
patent: 6040203 (2000-03-01), Bozso et al.
patent: 6175160 (2001-01-01), Paniccia et al.
patent: 6222246 (2001-04-01), Mak et al.
patent: 6236079 (2001-05-01), Nitayama et al.
patent: 6265321 (2001-07-01), Chooi et al.
patent: 6271795 (2001-08-01), Lesea et al.
patent: 6281042 (2001-08-01), Ahn et al.
patent: 6281547 (2001-08-01), So et al.
patent: 6311313 (2001-10-01), Camporese et al.
patent: 6322903 (2001-11-01), Siniaguine et al.
patent: 6424034 (2002-07-01), Ahn et al.
patent: 6461895 (2002-10-01), Liang et al.
patent: 6495442 (2002-12-01), Lin et al.
patent: 6586835 (2003-07-01), Ahn et al.
patent: 2001/0006233 (2001-07-01), Vallett
patent: 2001/0040664 (2001-11-01), Tajima et al.
patent: 2002/0068441 (2002-06-01), Lin
patent: 2004/0166659 (2004-08-01), Lin et al.
patent: 2004/0173880 (2004-09-01), Achyut
patent: 254 046 (1988-01-01), None
patent: 280 848 (1988-08-01), None
patent: 2000-58545 (2000-02-01), None
E.A.M. Klumpernik et al., “Transmission Lines in CMOS: An Explorative Study”, 12thAnnual Workshop on Circuits, Systems and Signal Processing, Veldhove/Netherlands, Nov. 29-30, 2001, pp. 440-445.
Jim Lipman, Technical Editor, “Growing your own IC clock tree”, EDN Access—03.14.97 Growing your own IC clock tree, Jim Lipman, Technical Editor, “Growing your own IC clock tree”, EDN Access—03.14.97 Growing your own IC clock tree, http://archives.e-insite.net/archives/ednmag/reg/1997/031497/06CS.HTM, Feb. 27, 2002, pp. 1-7.
L. Cao and J.P. Krusius, A Novel “Double-Decker” Flip-Chip BGA Package for Lower Power Giga-Hertz Clock Distribution, 1997 47thElectronic Components and Technology Conference, San Jose, CA, 1152-1157 (May 16-21, 1997).
Flynn Nathan J.
MacPherson Kwok & Chen & Heid LLP
Sefer Ahmed W.
Shenker Michael
Tru-Si Technologies Inc.
LandOfFree
Clock distribution networks and conductive lines in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Clock distribution networks and conductive lines in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock distribution networks and conductive lines in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3838831