Clock distribution network with efficient shielding

Details Clock distribution network with efficient shielding Clock distribution network with efficient shielding

1996-07-01

1999-11-30

Arroyo, Teresa M.

Active solid-state devices (e.g., transistors, solid-state diode

With shielding

257630, 257208, 257211, 257758, H01L 23552, H01L 2358, H01L 2710, H01L 2348

Patent

active

059947659

ABSTRACT:
An interconnect structure includes in a first layer a clock line and a ground line running substantially parallel to the clock line, and a plurality of conductive regions lying in a second layer parallel to the first layer. The ground line is coupled to a source of ground potential. The conductive regions are aligned with the clock line and are disposed around a signal line routed in the second layer across the clock line. The conductive regions are electrically connected to the ground line, thereby forming a shield for the clock line that helps prevent clock signals propagated on the clock line from electromagnetically coupling with other signal lines. In one embodiment, a clock distribution network includes conductive regions (501, 503, 505. . . ) in the metal layer below the clock line layer and two parallel ground lines (201, 203) in the same metal layer as the clock line (101). The conductive regions (501, 503, 505 . . .) are electrically connected to the ground lines (201, 203) with vias (603A, 603B, 605A, 605B . . . ). In the same metal layer as the conductive regions, conductive signal lines (509, 511) are routed between the regions (501, 503, 505, 507. . . ) to cross below the clock line. The conductive regions (501, 503, 505, 507. . . ) form a shield between the clock line (101) and any signal lines (105) routed in the next metal layer adjacent to the metal layer containing the conductive regions.

REFERENCES:
patent: 4032903 (1977-06-01), Weimer
patent: 4881250 (1989-11-01), Davids et al.
patent: 5223733 (1993-06-01), Doi et al.
patent: 5309015 (1994-05-01), Kuwata et al.

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