Clock distribution network having regulated power supply

Details Clock distribution network having regulated power supply Clock distribution network having regulated power supply

2000-12-28

2003-11-18

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S551000, C327S293000

Reexamination Certificate

active

06650161

ABSTRACT:

TECHNICAL FIELD OF INVENTION
The present invention relates generally to integrated circuit clocking, and more specifically, to distributing a clock throughout an integrated circuit system.
BACKGROUND OF THE INVENTION
An issue facing the integrated circuit industry today is the problem of distributing clock signals throughout integrated circuit systems and integrated “circuit dies with minimal clock delay variation and jitter. One source of clock ”; “variation and jitter is noise in the power supply to the inverters that drive the”; and clock signal throughout the integrated circuit. Currently, the amount of clock delay variation and jitter due to power supply noise is dealt with by lowering the maximum chip operating frequency to provide a higher margin for clock delay variation and jitter. Stated another way, because of the clock delay variation and jitter, the maximum operating frequency of the integrated circuit is reduced. Thus, by lowering the amount of clock delay variation and jitter, the maximum operating frequency of the integrated circuit can be increased.
In a conventional clock distribution network, a series of inverters are used, increasing in size, to drive the capacitance of the clock load starting at the clock generator circuit. One example of such a clock distribution network is described in U.S. Pat. No. 6,037,822 to Rao et al. and assigned to the same assignee as the present invention. In the '822 patent, inverters are used to drive a clock signal through an “H-tree” clock distribution system. Typically, the inverters are connected directly to the power supply of the integrated circuit. Noise in the power supply affects the performance of the inverters and results in clock variation and jitter at the peripheral boundaries of the clock distribution network. This tends to lower the maximum chip operating frequency. Specifically, as seen in
FIG. 1
, a power supply V
cc
101
powers an inverter
103
. The inverter
103
is one of many inverters that form the clock distribution network. As seen in
FIG. 1
, the power supply
101
is connected directly to the inverter
103
. It has been found that this direct connection of the power supply to the inverter
103
results in clock delay variation and jitter, if there is noise on the power supply.


REFERENCES:
patent: 5051630 (1991-09-01), Kogan et al.
patent: 5442304 (1995-08-01), Wong et al.
patent: 5627736 (1997-05-01), Taylor
patent: 5929679 (1999-07-01), Ohwada
patent: 6111448 (2000-08-01), Shibayama
patent: 6154100 (2000-11-01), Okamoto
patent: 6229861 (2001-05-01), Young

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