Clock distribution network for reducing clock skew

Details Clock distribution network for reducing clock skew Clock distribution network for reducing clock skew

1995-09-08

1997-08-12

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327292, 327293, 327565, 257208, 257786, H03K 19003

Patent

active

056569637

ABSTRACT:
A clock distribution network for distributing a clock signal across a VLSI chip. A H-tree is combined with an x-y grid to allow buffering of the clock signal, while minimizing clock skew across the chip. The H-tree distributes a plurality of repower buffer levels above a final repower buffering level. The output of the final level are coupled by the x-y grid to minimizes clock skew caused by the chip and by local loading variations in the circuits.

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