Clock distribution in a circuit emulator

Details Clock distribution in a circuit emulator Clock distribution in a circuit emulator

2006-10-03

2006-10-03

Shah, Kamini (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Emulation

Of peripheral device

C716S030000, C716S030000, C716S030000, C716S030000, C703S013000, C703S023000, C713S400000

Reexamination Certificate

active

07117143

ABSTRACT:
Before using a netlist description of an integrated circuit as a basis for programming a circuit emulator, a clock analysis tool analyzes the netlist to identify synchronizing circuits including clocked devices (“clock sinks”) such a flip-flops, registers and latches for synchronizing communication between blocks of logic within the IC. The tool initially classifies the clock signal input to each clock sink according to its clock domain, sub-domain and phase. The tool then classifies each synchronizing circuit according to relationships between the classifications of the clock signals it employs to clock its input and output clock sinks. The tool then determines, based on the classification of each synchronizing circuit, whether the emulator can reliably emulate that synchronizing circuit, or whether the tool should automatically modify the netlist description of the synchronizing circuit so that the emulator can emulate it. The tool also generates a warning when an emulator may not reliably emulate a synchronizing circuit and the tool cannot automatically modify it so that the emulator can reliably emulate it.

REFERENCES:
patent: 6009531 (1999-12-01), Selvidge et al.
patent: 6301553 (2001-10-01), Burgun et al.
patent: 7003746 (2006-02-01), Hyduke et al.

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