Clock distribution for 10GBase-T analog front end

Details Clock distribution for 10GBase-T analog front end Clock distribution for 10GBase-T analog front end

2011-07-19

2011-07-19

Puente, Eva Y (Department: 2611)

Pulse or digital communications

Synchronizers

Network synchronizing more than two stations

C375S375000, C375S258000, C375S354000, C375S348000, C370S294000

Reexamination Certificate

active

07983373

ABSTRACT:
A 10GBASE-T clocking method that limits EMI and increases SNR, while reducing power and conserving chip space is provided. The method includes simultaneous clocking of transmitters in an analog front end of a 10 gigabit Ethernet. The method includes providing at least two channels to a 10GBase-T analog front end, where the channel has at least a transmitter port and a receiver port, and providing at least two phase interpreters to the analog front end, where each phase interpreter is dedicated to one receiver port. A central clock generator is disposed to distribute a transmit clock to the phase interpreters and to the transmitter ports, where the transmit clock is further provided to the receiver ports from the phase interpreters. Any clock delay between the clock generator and each channel is balanced and clock phases between the channels are matched.

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