Clock distribution circuit with clock branch circuits connected

Details Clock distribution circuit with clock branch circuits connected Clock distribution circuit with clock branch circuits connected

1996-11-26

1999-04-20

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327293, 327284, 326 93, H03K 300

Patent

active

058960554

ABSTRACT:
A layout area includes a clock interconnection consisting of an upward interconnection and a downward interconnection. The upward interconnection extends from the output terminal of a clock buffer which receives an external clock signal to a turning point while passing along the vicinity of a plurality of flip-flops. The downward interconnection extends from the turning point to a free end, reversing along the upward interconnection. Clock branch circuits are provided in the vicinity of the flip-flops. The clock branch circuits have a function of letting a third clock signal make a transition when the sum of the time integral of a first clock signal on the upward interconnection and the time integral of a second clock signal on the downward interconnection has become equal to the time integral for one pulse of one of the first clock signal and the second clock signal.

REFERENCES:
patent: 4514749 (1985-04-01), Shoji
patent: 4998262 (1991-03-01), Wiggers
patent: 5045725 (1991-09-01), Sasaki et al.
patent: 5307381 (1994-04-01), Ahuja
patent: 5361277 (1994-11-01), Grover
patent: 5398262 (1995-03-01), Ahuja
patent: 5432823 (1995-07-01), Gasbarro et al.
patent: 5528187 (1996-06-01), Sato et al.

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