Clock distribution circuit in an integrated circuit

Details Clock distribution circuit in an integrated circuit Clock distribution circuit in an integrated circuit

1998-12-21

2001-06-26

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

Reexamination Certificate

active

06252449

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of integrated circuits and, more specifically, integrated circuits comprising, on the one hand, internal logic circuits and, on the other hand, a clock signal distribution circuit for driving these logic circuits.
2. Discussion of the Related Art
In conventional integrated circuits, it is generally attempted to decrease the power consumed. The power consumption of circuits sometimes becomes one of the main criteria in their definition, for example, in applications powered by a battery having a limited lifetime.
To achieve this object, a present tendency is to decrease the supply voltage of integrated circuits. In logic integrated circuits (or integrated circuits including logic circuits) driven by a clock signal, this tendency to decrease the supply voltage increases with the general desire to increase the frequency of the clock signal driving these circuits. Now, the power consumed by these circuits is also proportional to the clock signal frequency.
The decrease of the supply voltage generally raises problems in the definition of the integrated circuits. Indeed, new methods which minimize the sources of losses, such as, for example, the transistor threshold voltages, often have to be developed. Such new methods are generally more complex, and thus more difficult to implement and costly in terms of development and/or production. It can further be attempted to improve the circuits, to decrease their power consumption. In the same way as for the definition of new methods, this circuit optimization can be difficult and result in higher development and/or production costs.
SUMMARY OF THE INVENTION
An aim of the present invention is to provide a solution to minimize or reduce the power consumed in logic circuits, or in circuits including logic circuits, and which is easily implementable and of low cost.
For this purpose, it is provided, for an operation of the logic circuits at a given frequency, said operation being driven by a clock signal, to provide the desired frequency only locally, at the level of the logic circuits meant to operate at said frequency, and to decrease the frequency in the clock distribution circuits. Thus, for a given supply voltage, the power consumption induced by the clock distribution circuits is reduced or minimized, and the general power consumption of the integrated circuits is thus also reduced. This reduction of the power consumption is all the more important as, generally, clock distribution circuits physically extend across all logic integrated circuits, from one or two peripheral connections receiving an external clock signal or connected to the terminals of an external quartz crystal oscillator. The distribution of the external clock signal (or of an internal clock signal generated locally from the quartz crystal oscillator) is performed via conductive lines forming a tree structure extending across the circuit. The conductive lines have an equivalent stray capacitance which increases as the surface area of the integrated circuit increases the power consumption induced by such a distribution circuit is proportional to the equivalent capacitance. Power consumption thus becomes significant for present circuits, in which it is desired to integrated more and more functions, which results in an increase in the circuit surface area.
Thus, the present invention relates to an integrated circuit including at least one logic circuit, able to operate at a first operating frequency, and a clock distribution circuit, the clock distribution circuit receiving a first clock signal and providing to the logic circuit a second clock signal, generated based on the first clock signal, the frequency of the second clock signal being substantially equal to the first operating frequency. The clock distribution circuit includes a frequency multiplying circuit for generating the second clock signal, so that the frequency of the first clock signal may be lower than the first operating frequency to reduce or minimize the power consumed by the clock distribution circuit.
According to an embodiment, the clock distribution circuit includes a frequency dividing circuit for generating, from the first clock signal, a clock signal internal to the clock distribution circuit, the internal clock signal having a frequency lower than the frequency of the first clock signal, to reduce or minimize the power consumed by the clock distribution circuit.
According to an embodiment, the frequency multiplying circuit includes control means for maintaining the second clock signal in a permanent state, to reduce or minimize the power consumed by the logic circuit.
According to an embodiment, the frequency multiplying circuit receives an input clock signal. It includes, on the one hand, delay means for generating, by time dephasing, based on the input clock signal, a delayed clock signal and, on the other hand, logic means for generating the second clock signal by performing a logic combination of X-OR type between the input clock signal and the delayed clock signal.
According to an embodiment, the frequency multiplying circuit includes means for modifying the time dephasing applied to the input clock signal.
According to an embodiment, the frequency multiplying circuit includes, on the one hand, several delay means for generating, by time dephasing, several delayed signals and, on the other hand, selection means for combining the input clock signal with one of the delayed signals.
According to an embodiment, the logic circuit being supplied by a first supply potential, the clock distribution circuit is partly supplied by a second supply potential, of a value lower than the value of the first supply potential, to reduce or minimize the power consumed by the clock distribution circuit.
According to an embodiment, the logic means of the frequency multiplying circuit are supplied by the first supply potential and the other elements of the clock distribution circuit are supplied by the second supply potential.


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