Clock distribution circuit in a semiconductor integrated circuit

Details Clock distribution circuit in a semiconductor integrated circuit Clock distribution circuit in a semiconductor integrated circuit

1998-05-27

2000-03-14

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327295, H03K 19096

Patent

active

060378204

ABSTRACT:
A clock distribution circuit reliably reduces clock skew, while preventing the waveform of a clock signal from rounding, which would otherwise occur due to an increase in resistance, and preventing instability of the clock signal, which would otherwise occur due to an increase in inductance, thereby realizing ideal clock distribution. In the clock distribution circuit, a clock wiring pattern for distributing the clock signal is formed on a chip, and a wiring pattern whose resistance is lower than the clock wiring pattern is formed on a substrate, on which the chip is mounted, in such a way as to be connected to the clock wiring pattern at a plurality of locations. The clock distribution circuit is applied to semiconductor integrated circuits such as LSIs built in multichip modules.

REFERENCES:
patent: 5521541 (1996-05-01), Okamura
patent: 5691662 (1997-11-01), Soboleski et al.

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