Clock distribution circuit for semiconductor integrated circuit

Details Clock distribution circuit for semiconductor integrated circuit Clock distribution circuit for semiconductor integrated circuit

1998-07-07

2000-03-28

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Integrated structure

327295, H01L 2500

Patent

active

060437049

ABSTRACT:
The invention provides a clock distribution circuit which can be applied readily also to a chip (semiconductor integrated circuit) of the building block type and can realize reduction in skew. The clock distribution circuit includes a first buffer disposed at a central location of the chip for receiving an output of an input driver, four second buffers individually disposed at central locations of four sides of the chip for receiving an output of the first buffer, a plurality of third buffers for receiving outputs of the second buffers, and a last stage connection wiring line system for connecting all of outputs of the third buffers commonly to extract a clock signal to be supplied to clock terminals. The third buffers are disposed on linear lines parallel to the two upper and lower sides of the chip, and the outputs of the third buffers are connected to each other by linear wiring lines. The clock distribution circuit further includes a load adjustment structure for adjusting a load to the first buffer or/and each of the second buffers. The present invention can be applied to a chip of the building block type which includes a RAM or a large number of huge macro blocks and the like.

REFERENCES:
patent: 5140184 (1992-08-01), Hamamoto et al.
patent: 5172330 (1992-12-01), Watanabe et al.
patent: 5239215 (1993-08-01), Yamaguchi
patent: 5430397 (1995-07-01), Itoh et al.
patent: 5668484 (1997-09-01), Nomura

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