Clock distribution circuit and test method

Details Clock distribution circuit and test method Clock distribution circuit and test method

2007-09-25

2010-06-08

Nguyen, Vincent Q (Department: 2831)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

C327S295000

Reexamination Certificate

active

07733079

ABSTRACT:
A clock distribution circuit having plural stages of buffers disposed along branch paths for dividing up a clock signal and configured in a manner that outputs of a plurality of buffers in a final stage and/or a middle stage are short-circuited, includes in relation to at least one buffer of a plurality of buffers in the same stage on a branch path, a selector for receiving an output of an adjacent buffer located upstream in terms of chain-connection along which the plurality of buffers are connected in testing, and a signal at a branch node corresponding to the at least one buffer by a first input and a second input respectively, selecting one of the first input and the second input based on a select control signal, and supplying the selected input to the one buffer.

REFERENCES:
patent: 2005/0134353 (2005-06-01), Tahara
patent: 2003-92352 (2003-03-01), None

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