Clock distribution circuit

Details Clock distribution circuit Clock distribution circuit

2009-03-06

2010-10-05

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S291000, C327S276000

Reexamination Certificate

active

07808293

ABSTRACT:
A clock distribution circuit includes a monitoring circuit that delays a signal based on a clock signal from a clock tree by using multiple inverter circuits and predicts a timing violation on the basis of the amount of delay produced by the multiple inverter circuits. The clock distribution circuit further includes an OR circuit that controls, on the basis of the result of prediction by the monitoring circuit, a clock gating signal generated by a combinational circuit and a clock gating circuit that supplies a clock signal or stops supply of the clock signal depending on a signal output from the OR circuit.

REFERENCES:
patent: 5491442 (1996-02-01), Mirov et al.
patent: 7023252 (2006-04-01), Schultz
patent: 7317342 (2008-01-01), Saint-Laurent
patent: 2006-3249 (2006-01-01), None
Shidhartha Das, et al., “A Self-Tuning DVS Processor Using Delay-Error Detection and Correction”, 2005 Symposium on VLSI Circuits Digest of Technical Papers, pp. 258-261.
U.S. Appl. No. 12/483,445, filed Jun. 12, 2009, Fujisawa.

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