Clock distribution circuit

Details Clock distribution circuit Clock distribution circuit

2011-08-09

2011-08-09

Nguyen, Hai L (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S293000, C327S295000

Reexamination Certificate

active

07994838

ABSTRACT:
A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values.

REFERENCES:
patent: 3654394 (1972-04-01), Gordon
patent: 4165490 (1979-08-01), Howe et al.
patent: 4390988 (1983-06-01), Best et al.
patent: 5075566 (1991-12-01), Chuang et al.
patent: 5087829 (1992-02-01), Ishibashi et al.
patent: 5122679 (1992-06-01), Ishli et al.
patent: 5307381 (1994-04-01), Ahuja
patent: 5444407 (1995-08-01), Ganapathy et al.
patent: 6028463 (2000-02-01), Albu et al.
patent: 6081145 (2000-06-01), Bandai et al.
patent: 6340905 (2002-01-01), Schultz
patent: 6535038 (2003-03-01), Hofstra
patent: 6653877 (2003-11-01), Tsujino
patent: 6677792 (2004-01-01), Kwak
patent: 6768361 (2004-07-01), Kwak
patent: 6812777 (2004-11-01), Tamura et al.
patent: 6907584 (2005-06-01), Milne et al.
patent: 6943610 (2005-09-01), Saint-Laurent
patent: 7227809 (2007-06-01), Kwak
patent: 7307461 (2007-12-01), Nguyuen et al.
patent: 7489176 (2009-02-01), Kaviani et al.
patent: 2004/0150453 (2004-08-01), Farjad-rad
Lee, M.E., et al., “Low-Power Area-Efficient High-Speed I/O Circuit Techniques,” IEEE J. of Solid-State Circuits, vol. 35, No. 11, Nov. 2000, pp. 1591-1599.
Van De Beek, R.C.H., et al., “Low-Jitter Clock Multiplication: A Comparison Between PLLs and DLLs,” IEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 49, No. 8, Aug. 2002, pp. 555-556.
Wang, Y.M., et al., “A Low-Power Half-Delay-Line Fast Skew-Compensation Circuit,” IEEE J. of Solid-State Circuits, vol. 39, No. 6, Jun. 2004, pp. 906-918.
Weinlader, D.K., “Precision CMOS Receivers for VLSI Testing Applications,” Doctoral Dissertation, Stanford University, Nov. 2001.

Affiliated with

Also associated with

Rating

Clock distribution circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock distribution circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock distribution circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2724393