Clock distribution architecture and method for high speed CPLDs

Details Clock distribution architecture and method for high speed CPLDs Clock distribution architecture and method for high speed CPLDs

1996-04-01

1998-10-13

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327 29, 327296, 327407, H03K 104

Patent

active

058217940

ABSTRACT:
The present invention provides a clocking circuit allowing individual macrocells in a particular macrocell block of a CPLD to use different polarities of the same clock. The input clock pin can now drive all the macrocells directly, which can eliminate additional buffering states and improve the clock to out timing, Tco, by (for example) 300 ps. The clocks are presented directly to the clock selection multiplexers for each macrocell. Additional functioning may be realized by implementing additional configuration bits inside the clocking architecture.

REFERENCES:
patent: 4229699 (1980-10-01), Frissell
patent: 4419629 (1983-12-01), O'Brien
patent: 4918641 (1990-04-01), Jigour et al.
patent: 4999526 (1991-03-01), Dudley
patent: 5510742 (1996-04-01), Lemaire
patent: 5589782 (1996-12-01), Sharpe-Geisler
patent: 5652536 (1997-07-01), Nookala et al.

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