Clock distributing logic and clock skew control design method fo

Details Clock distributing logic and clock skew control design method fo Clock distributing logic and clock skew control design method fo

1995-03-20

1997-05-06

Heckler, Thomas M.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Converting, per se, of an ac input to corresponding dc at an...

327261, G06F 104

Patent

active

056280009

ABSTRACT:
A clock distributing logic for distributing a clock signal in a circuit and reducing clock skew which occurs during the distributing of the clock signal in the circuit and a method for designing the same. The clock distributing logic includes at least two stages of clock amplifying gates for distributing the clock signal to source and sink sides of the circuit. Each of the at least two stages are successively connected to each other. Further, each of the at least two stages except a last stage includes clock amplifying gates of a same size providing a same driving ability. The last stage of clock amplifying gates includes clock amplifying gates of different sizes providing different driving abilities. The size of each clock amplifying gate of the last stage of clock amplifying gates is set to make the delay in distributing the clock signal in the circuit coincide with a desired clock signal distributing cycle.

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Exact Zero Skew, Ren-Song Tsay, IBM, T.J. Watson Research Center IEEE, 1991, pp. 336-339.

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