Clock distributing circuit in programmable logic device

Details Clock distributing circuit in programmable logic device Clock distributing circuit in programmable logic device

2001-03-29

2003-03-25

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S296000, C327S293000, C326S028000

Reexamination Certificate

active

06538489

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a clock distributing circuit in a programmable logic device (PLD), and more particularly to a clock distributing circuit in a programmable logic device wherein several types of clocks are input into one chip.
BACKGROUND OF THE INVENTION
A programmable logic device (PLD) is a logic LSI such that a user can program (externally set or rewrite) a combination of a plurality of logic circuits to obtain a necessary logical function. In recent years, a significant increase in scale of gates has made it possible to realize a circuit on a system level by a programmable logic device having a one-chip construction. For this reason, it is common practice to input several types of clocks into one chip.
The distribution of clocks in the programmable logic device has been performed through specialty wiring for speed increase purposes. An increase in the number of clocks, however has led to an increase in clock wiring area which is becoming an obstacle to an improvement in integration density and performance of devices.
FIG. 5
shows a first example of the conventional clock distributing circuit for a programmable logic device.
The clock distributing circuit shown in
FIG. 5
has a construction such that clock lines
201
a
,
201
b
,
201
c
,
201
d
respectively for a plurality of clocks (CLK-A, CLK-B, CLK-C, CLK-D) are wired in a plurality of routes (3 routes in this case), and clock buffers
202
a
to
2021
are connected to the inlets of the routes. Selectors
204
a
to
204
c
are connected to clock lines
203
a
to
203
d
for the clock buffers
202
a
to
202
d
, selectors
204
d
to
204
f
are connected to clock lines
203
e
to
203
h
, and selectors
204
g
to
204
i
are connected to clock lines
203
i
to
2031
. Further, flip-flops (FFs)
205
a
to
205
i
as logic circuits are connected to selectors
204
a
to
204
i
. A user controls the selectors
204
a
to
204
i
through a program, inputs one clock selected from four clocks in each of selectors
204
a
to
204
i
into respective flip-flops
205
a
to
205
i
. Flip-flops operated by a common clock on a common clock line constitute one logic circuit.
FIG. 6
shows a second example of the conventional clock distributing circuit for a programmable logic device.
According to the construction of this clock distributing circuit clocks can be fed to flip flops without use of separate selectors. This clock distributing circuit is described in more detail in Japanese Patent Laid-Open No. 120811/1994. In this construction, programmable connector elements are used instead of the selectors
204
a
to
204
i
shown in FIG.
5
. Specifically, connector elements
206
a
to
206
d
are used instead of the selector
204
a
, connector elements
207
a
to
207
d
are used instead of the selector
204
b
, connector elements
208
a
to
208
d
are used instead of the selector
204
c
, connector elements
209
a
to
209
d
are used instead of the selector
204
d
, connector elements
210
a
to
210
d
are used instead of the selector
204
e
, connector elements
211
a
to
211
d
are used instead of the selector
204
f
, connector elements
212
a
to
212
d
are used instead of the selector
204
g
, connector elements
213
a
to
213
d
are used instead of the selector
204
h
, and connector elements
214
a
to
214
d
are used instead of the selector
204
i.
Each of the connector elements
206
a
to
214
d
comprises a memory cell for holding program data and a transistor which functions as a switching element. When only one of the connector elements
206
a
to
206
d
is turned on, only one clock selected from CLK-A to CLK-D is input into the corresponding flip-flop. This is true of the connector elements
207
a
to
207
d
,
208
a
to
208
d
,
209
a
to
209
d
,
210
a
to
210
d
,
211
a
to
211
d
,
212
a
to
212
d
,
213
a
to
213
d
, and
214
a
to
214
d.
In the prior art a plurality of circuits for incorporating clocks into clock feed means, such as clock buffers, are present in a programmable logic device. Further, it is known that, for each of the circuits, when the wiring length between the circuit and the clock feed means is not identical, a phenomenon called “clock skew” takes place wherein a difference in clock arrival time occurs. The clock skew becomes more significant with increasing the clock rate and with increasing the programmable array density, and is an obstacle to an increase in speed of logical operation. For this reason, the clock skew should be minimized.
The circuits shown in
FIGS. 5 and 6
will be reviewed. In the construction shown in
FIG. 5
, selectors are provided close to respective flip-flops, and all the clock lines are connected to the selectors. Therefore, the clock skew is small. Since, however, this construction requires wiring of all the clock lines, the clock line wiring area is large. On the other hand, in the construction shown in
FIG. 6
, each flop-flop is connected to four clock lines (such as
203
a
to
203
d
) through a single clock incorporation line. This can reduce the necessary area for wiring between four clock lines and each flip-flop, but on the other hand, the clock skew is increased.
Several proposals have hitherto been made as means for reducing clock skew. For example, Japanese Patent Laid-Open No. 317457/1999 proposes a method wherein in addition to a basic logic circuit, a dummy load is connected to the output side of a clock driver as clock feed means, the minimum dummy load capacity necessary for equalizing the total load of clock signals is calculated for each circuit arrangement area, and this is disposed in the circuit arrangement area, and, in addition, clock wiring and signal wiring are performed to connect the basic logic circuit to the dummy load.
According to the conventional clock distributing circuit in a programmable logic device (PLD) in PLDs having constructions shown in
FIGS. 5 and 6
, a plurality of clock lines corresponding to the number of clocks are wired so as to spread to all the flip-flops. This increases the wiring area for clock lines and thus limits the space for mounting elements.
Further, the method disclosed in Japanese Patent Laid-Open No. 317457/1999 requires high accuracy on the distance to each clock driver and, in addition, requires high accuracy on the distance to circuits behind the clock drivers. Therefore, the degree of freedom is low. Further, in this method. the total number (N) of circuits connected to the clock driver (flip-flops+dummy loads) is made constant so that N circuits are equally connected to each clock driver. This method, however, is not intended for PLD and a plurality of clocks. Therefore, it is difficult to apply this technique to circuits having a construction using PLD and a plurality of clocks such that, in elements wherein a plurality of clock signal distribution paths are not even, a user controls connector elements through programming.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a clock distributing circuit in a programmable logic device which can reduce the necessary wiring area for clock lines.
It is another object of the invention to provide a clock distributing circuit in a programmable logic device which can reduce the necessary wiring area for clock lines and, in addition, can suppress an increase in skew.
According to the first feature of the invention, a clock distributing circuit in a programmable logic device (PLD), for selecting one clock from a plurality of clocks and then feeding the selected clock to a plurality of logic circuits, comprises:
a clock generation source for generating the plurality of clocks;
select signal generation means for generating a select signal for selecting one clock from the plurality of clocks based on a program; and
a selector for selecting one clock from the plurality of clocks based on the select signal and feeding the selected clock to logic circuits selected from the plurality of logic circuits.
According to this construction, a select signal in selecting one of a plurality of clo

Affiliated with

Also associated with

Rating

Clock distributing circuit in programmable logic device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock distributing circuit in programmable logic device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock distributing circuit in programmable logic device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3013277