Clock deskew protocol using a delay-locked loop

Details Clock deskew protocol using a delay-locked loop Clock deskew protocol using a delay-locked loop

2005-03-01

2005-03-01

Tan, Vibol (Department: 2819)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S144000, C327S158000, C327S161000

Reexamination Certificate

active

06861886

ABSTRACT:
A data/clock deskewing methodology uses a delay-locked loop (DLL) circuit. The DLL circuit generates a number of clock phases in response to an input clock, where each clock phase is delayed relative to the input clock signal. The clock phases are used to sample data from a data line. The sampled data is checked against a preamble pattern (a sequence of known data). A digital deskew control block selects one of the clock phases after analyzing the results of preamble pattern check such that subsequently received data is sampled with the appropriately selected clock phase.

REFERENCES:
patent: 6366145 (2002-04-01), Williams et al.
patent: 6429715 (2002-08-01), Bapat et al.
patent: 6686785 (2004-02-01), Liu et al.
patent: 6693985 (2004-02-01), Li et al.
K. Lee et al., “1.04 GBd Low EMI Digital Video Interface System Using Small Swing Serial Link Technique”, IEEE Journal of Solid-State Circuits, vol. 323, No. 5, May 1998.

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