Clock delay trim adjustment with stopping feature for eliminatin

Details Clock delay trim adjustment with stopping feature for eliminatin Clock delay trim adjustment with stopping feature for eliminatin

1992-06-30

1993-11-30

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 307262, 307261, 307603, 328 63, H04N 504

Patent

active

052668509

ABSTRACT:
Method and circuitry for phase synchronizing an analog input signal with a clock signal by sensing clock delay error, adjusting in increments clock delay trim of a delay element that initially has an arbitrary delay setting, and stopping adjustment after differential delay between the signals has been eliminated.

REFERENCES:
patent: 4030038 (1977-06-01), Daniel et al.
patent: 4546269 (1985-10-01), Johnson
patent: 4578705 (1986-03-01), Elmis et al.
patent: 4839726 (1989-06-01), Balopole et al.
patent: 4945538 (1990-07-01), Patel
patent: 5087829 (1992-02-01), Ishibashi et al.

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