Clock delay compensation circuit

Details Clock delay compensation circuit Clock delay compensation circuit

2006-12-19

2006-12-19

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S262000

Reexamination Certificate

active

07151396

ABSTRACT:
A clock delay compensation circuit for an integrated circuit having a first voltage domain and a second voltage domain, has a first delay element that receives a clock signal and generates a first delayed clock signal, and a multiplexer that receives the clock signal and the first delayed clock signal and generates a variable clock signal. The first delayed clock signal is selected when the second voltage domain is at a higher voltage level than the first voltage domain.

REFERENCES:
patent: 6262616 (2001-07-01), Srinivasan et al.
patent: 6529058 (2003-03-01), Gupta
patent: 6603340 (2003-08-01), Tachimori
patent: 6624680 (2003-09-01), Schenck
patent: 6657473 (2003-12-01), Eto
patent: 6664838 (2003-12-01), Talledo
patent: 6664850 (2003-12-01), Roy
patent: 6788123 (2004-09-01), Roy

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