Clock delay circuitry producing clock delays less than the...

Details Clock delay circuitry producing clock delays less than the... Clock delay circuitry producing clock delays less than the...

1998-05-21

2001-02-06

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular frequency control means

C331S00100A, C327S261000, C327S269000, C327S270000, C327S159000, C327S160000

Reexamination Certificate

active

06184753

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to clock delay circuitry incorporated into integrated circuits or the like and suitable for generating an internal clock signal in synchronization with an external clock signal applied thereto, and to oscillation circuitry, phase synchronization circuitry, and clock generating circuitry using the clock delay circuitry. More particularly, it relates to clock delay circuitry capable of setting and providing a time delay in steps of a specified time interval which cannot be restricted by a minimum of time delays provided by discrete circuit elements and transistors, and which is less than the minimum time delay, and to an oscillation circuit, a phase locked loop, and a clock generating circuit using the clock delay circuit.
2. Description of the Prior Art
Referring now to
FIG. 11
, there is illustrated a block diagram showing a clock generating circuit which can be contained on integrated circuits, as disclosed by “A Full-Digital PLL for LOW Voltage LSIs”, TECHNICAL REPORT OF IEICE, Vol. 97, No. 106, pp. 29-36, June, 1997. In the figure, reference numeral
12
denotes an oscillation circuit for multiplying the frequency of a reference clock signal applied thereto and for furnishing a multiplied clock signal having the multiplied frequency, and
13
denotes a phase synchronization circuit for delaying the multiplied clock signal from the oscillation circuit
12
by a specified time interval and for furnishing a phase locked clock signal exactly in phase with the reference clock signal.
Reference numeral
14
denotes a loop inverter for inverting the multiplied clock signal,
16
denotes a first digital delay line (DLL) for delaying the output of the loop inverter
14
by a specified time interval defined by a delay setting signal applied thereto, and
51
denotes a delay adjustment circuit for delaying the output of the first DLL by a specified time interval defined by a delay setting signal applied thereto and for furnishing its output to the phase synchronization circuit
13
as the multiplied clock signal. Hereafter, the delay loop constructed of these circuits
14
,
16
, and
51
is referred to as multiplication delay loop.
Furthermore, reference numeral
19
denotes a first phase comparator which accepts the multiplied clock signal from the delay adjustment circuit
51
and the reference clock signal and then compares the phase of the reference clock signal with that of the multiplied clock signal so as to generate a first phase difference signal indicating the phase difference between the multiplied clock signal and the reference clock signal, and
20
denotes a first delay time setting circuit for generating and furnishing first delay setting signals each having a value that depends on the phase difference indicated by the first phase difference signal from the first phase comparator
19
to both the first DLL
16
and the delay adjustment circuit
51
. The oscillation circuit
12
is thus comprised of the loop inverter
14
, the first DDL
16
, the delay adjustment circuit
51
, the first phase comparator
19
, and the first delay setting circuit
20
.
Reference numeral
24
denotes a second digital delay line or DDL comprised of a plurality of delay elements in series, for delaying the multiplied clock signal from the delay adjustment circuit
51
by a specified time interval defined by a delay setting signal applied thereto and for generating a phase locked clock signal in phase with the reference clock signal,
26
denotes a second phase comparator which accepts the reference clock signal and the phase locked clock signal from the second DDL
24
and compares the phase of the reference clock signal and that of the phase locked clock signal so as to generate a second phase difference signal indicating the phase difference between these clock signals, and
27
denotes a second delay setting circuit for generating and furnishing a second delay setting signal having a value defined by the second phase difference signal from the second phase comparator
26
to the second DDL
24
to set the time delay to be provided by the second DDL
24
. The phase synchronization circuit
13
is thus comprised of the second DDL
24
, the second phase comparator
26
, and the second delay setting circuit
27
.
Referring next to
FIG. 12
, there is illustrated a schematic circuit diagram showing the structures of the delay adjustment circuit
51
and the first DDL
16
. In the figure, reference numeral
52
denotes a DDL delay element which constructs part of the first DDL
16
,
53
denotes an delay adjustment element which provides the same time delay as each of the plurality of delay elements
52
, and
54
denotes an output selector which accepts both the output of the first DDL
16
and the output of the delay adjustment element
53
and then selects and furnishes one of them according to a switching signal applied thereto. Like the first DDL
16
, the second DDL
24
includes a plurality of DDL delay elements
52
in series.
In operation, when the loop inverter
14
receives a falling edge of the multiplied clock signal from the delay adjustment circuit
51
, the delay adjustment circuit
51
will furnish a rising edge of the multiplied clock signal after the expiration of a predetermined time interval. Similarly, when the loop inverter
14
receives a rising edge of the multiplied clock signal from the delay adjustment circuit
51
, the delay adjustment circuit
51
will furnish a falling edge of the multiplied clock signal after the expiration of a predetermined time interval. The multiplied clock signal generated by the multiplication delay loop, which is constructed of the loop inverter
14
, the first DDL
16
, and the delay adjustment circuit
51
, is thus a clock signal in which a transition from HIGH to LOW or from LOW to HIGH is repeated at established intervals having the same length as the time delay produced by the multiplication delay loop, with the result that the multiplied clock signal from the delay adjustment circuit
51
has a period two times as long as the time delay provided by the multiplication delay loop.
When the oscillation circuit
12
receives the reference clock signal while the multiplication delay loop, which is constructed of the loop inverter
14
, the first DDL
16
, and the delay adjustment circuit
51
, operates in this manner, the first phase comparator
19
compares the phase of the reference clock signal with that of the multiplied clock signal from the delay adjustment circuit
51
and then generates a first phase difference signal indicating the phase difference between these signals. The first delay setting circuit
20
then generates first delay setting signals for setting the respective time delays produced by the first DDL
16
and the delay adjustment circuit
51
so as to reduce the phase difference.
Referring next to
FIG. 13
, there is illustrated a timing diagram showing an example of the operation of the prior art oscillation circuit
12
. In the example shown in
FIG. 13
, the frequency of the multiplied clock signal is set to be four times as large as that of the reference clock signal. As shown in
FIG. 13
, a switching signal for causing the output selector
54
to switch the selection from the output of the first DDL
16
to the output of the delay adjustment element
53
is applied to the output selector
54
of the delay adjustment circuit
51
after the expiration of a three quarters part of the pulse duration of the reference clock signal since the rising edge of the reference clock signal. As a result, the time delay caused by the multiplication delay loop is changed to {(n+1)×&Dgr;d}, where &Dgr;d is the time delay provided by either one of each delay element
52
and the delay adjustment element
53
, and n×&Dgr;d is the immediately previous time delay caused by the multiplication delay loop.
As previously explained, the prior art oscillation circuit
12
can generate a multiplied clock signal having a frequenc

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